hon829

回覆 10# clcwong


先看看別人解釋兩種output電路結構吧
http://cary1120.blogspot.com/2013/11/open-drain-push-pull.html

不要將TTL Logic Level的uncertain範圍看成是random/noise  voltage

icefire

1. 換句話講   即係理論上接每粒logic IC都應該要有一個pull-up/down resistor for each input pin?

2. ...
clcwong 發表於 2019-12-28 21:38

1. 唔好成日講到一定要點, 真係好睇你做咩, 我好多時enable pin先pull low/down, 因為pull up會食電
3. 係
4. 成條2.54mm jump wire駁左出來, 仲駁埋入bread board都唔叫長?  成條天線, 果度夠induce市電50Hz落去.

concept係
樣樣野放落電子線路都有Parasitic element, 有impedance(L/C/R). 大氣有電阻值, PCB板有電阻值, 只係大定細, 有resistance, 電流就會leak. 兩條電線放得近己經係一個capacitor同transformer, 只係數值微細, 但有capacitance/inductance, 就可以induce voltage
加電阻pull up/high就係控制impedance, 電阻impedance值 <<< Parasitic element值

燕飛

呢個我都理解   加上下拉電阻只係幫佢set一個default logic level   係無輸入時達到一個default既邏輯電 ...
clcwong 發表於 2019-12-28 22:27

正常"有用"的circuit 多不需要pull-up/down
9成有另一隻IC drive條pin

eeek

回覆 1# clcwong

唔怕麻煩嘅話, 可以買粒 74HC logic gate (e.g. 74HC04) 砌個簡單 circuit (e.g. output 接粒 3mm 細電流 Red LED + 220ohm 限流電阻; LED on/off 用作 output high/low indicator) 做下實驗.